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?2007 silicon storage technology, inc. s71299-03-000 7/07 1 the sst logo and superflash are registered trademarks of silicon storage technology, inc. mpf+ and combomemory are trademarks of silicon storage technology, inc. these specifications are subject to change without notice. preliminary specifications features: ? combomemories organized as: ? sst32hf64a2: 4m x16 flash + 1024k x16 psram ? single 2.7-3.3v read and write operations ? concurrent operation ? read from or write to psram while erase/program flash ? superior reliability ? endurance: 100,000 cycles (typical) ? greater than 100 years data retention ? low power consumption: ? active current: 15 ma (typical) for flash or psram read ? standby current: 60 a (typical) ? flexible erase capability ? uniform 2 kword sectors ? uniform 32 kword size blocks ? erase-suspend/erase-resume capabilities ? security-id feature ? sst: 128 bits; user: 128 bits ? fast read access times: ? flash: 70 ns ? psram: 70 ns ? hardware block-protection/wp# input pin ? top block-protection (top 32 kword) for sst32hf64a2 ? latched address and data for flash ? flash fast erase and word-program: ? sector-erase time: 18 ms (typical) ? block-erase time: 18 ms (typical) ? chip-erase time: 40 ms (typical) ? word-program time: 7 s (typical) ? flash automatic erase and program timing ? internal v pp generation ? flash end-of-write detection ? toggle bit ? data# polling ? cmos i/o compatibility ? jedec standard command set ? package available ? 56-ball lfbga (8mm x 10mm x 1.4mm) ? 64-ball lfbga (8mm x 10mm x 1.4mm) ? all non-pb (lead-free) devices are rohs compliant product description the sst32hf64a2 combomemory device integrates a cmos flash memory bank with a cmos pseudosram (psram) memory bank in a multi-chip package (mcp), manufactured with sst proprietary, high-performance superflash technology. featuring high-performance word-program, the flash memory bank provides a maximum word-program time of 7 sec. to protect against inadvertent flash write, the sst32hf64a2 device contains on-chip hardware and soft- ware data protection schemes. the sst32hf64a2 device offers a guaranteed endurance of 10,000 cycles, and data retention greater than 100 years. the sst32hf64a2 device c onsists of two independent memory banks, each with enable signals. the flash and psram memory banks are superimposed in the same memory address space, and both banks share common address lines, data lines, we# and oe#. the memory bank is selected using the memory bank enable signals. the psram bank enable signal, bes1#, selects the psram bank. the flash memory bank enable signal, bef#, selects the flash memory bank. the we# signal is used with the software data protection (sdp) command sequence when controlling the erase and program opera- tions in the flash memory bank. the sdp command sequence protects the data stored in the flash memory bank from accidental alteration. the sst32hf64a2 provides the added functionality of being able to simultaneously read from, or write to, the psram bank while erasing or programming in the flash memory bank. the psram memory bank can be read or written while the flash memory bank performs sector- erase, bank-erase, or word-program concurrently. all flash memory erase and prog ram operations will automati- cally latch the input address and data signals and complete the operation in background without further input stimulus required. once the internally controlled erase or program cycle in the flash bank commences, the psram bank can be accessed for read or write. multi-purpose flash plus + psram combomemory sst32hf64a2 sst32hf64a1 / 64b164mb flash + 4mb sram, 32mb flash + 8mb sram (x16) mcp combomemories
2 preliminary specifications multi-purpose flash plus + psram combomemory sst32hf64a2 ?2007 silicon storage technology, inc. s71299-03-000 7/07 the sst32hf64a2 device is suited for applications that use both flash memory and psram memory to store code or data, and is ideal for systems requiring low power and small form factor. the sst32hf64a2 significantly improves performance and reliability, while lowering power consumption, when compared with multiple chip solutions. the total energy consumed is a function of the applied volt- age, current, and time of application. since for any given voltage range, the superflash technology uses less cur- rent to program and has a shorter erase time, the total energy consumed during any erase or program operation is less than alternative flash technologies. the superflash technology provides fixed erase and pro- gram times, independent of the number of erase/program cycles that have occurred. therefore the system software or hardware does not have to be modified or de-rated as is necessary with alternative flash technologies, whose erase and program times increase with accumulated erase/pro- gram cycles. device operation the sst32hf64a2 uses bes1#, bes2 and bef# to con- trol operation of either the flash or the psram memory bank. when bef# is low, the flash bank is activated for read, program or erase operation. when bes1# is low and bes2 is high, the psram is activated for read and write operation. bef# and bes1# cannot be at low level, and bes2 cannot be at high level at the same time. if all bank enable signals are asserted, bus contention will result and the device may suffer permanent damage. all address, data, and control lines are shared by flash and psram memory banks which minimizes power consump- tion and loading. the device goes into standby when bef# and bes1# bank enables are raised to v ihc (logic high) or when bef# is high and bes2 is low. concurrent read/write operation the sst32hf64a2 provides the unique benefit of being able to read from or write to psram, while simultaneously erasing or programming the flash. this allows data alter- ation code to be executed from psram, while altering the data in flash. see figure 29 for a flowchart. the following table lists all valid states. the device will ignore all sdp commands when an erase or program operation is in progress. note that product identification commands use sdp; therefore, these com- mands will also be ignored while an erase or program operation is in progress. flash read operation the read operation of the sst32hf64a2 is controlled by bef# and oe#. both have to be low, with we# high, for the system to obtain data from the outputs. bef# is used for flash memory bank selection. when bef# is high, the chip is deselected and only standby power is consumed. oe# is the output control and is used to gate data from the output pins. the data bus is in high impedance state when oe# is high. refer to figure 7 for further details. flash word-program operation the flash memory bank of the sst32hf64a2 is pro- grammed on a word-by-word basis. before program opera- tions, the memory must be erased first. the program operation consists of three steps. 1. load the three-byte sequence for software data protection. 2. load word address and word data. during the word-program operation, the addresses are latched on the falling edge of either bef# or we#, whichever occurs last. the data is latched on the rising edge of either bef# or we#, whichever occurs first. 3. initiate the internal program operation after the rising edge of the fourth we# or bef#, whichever occurs first. the program operation, once initi- ated, will be completed, within 10 s. see figures 8 and 9 for we# and bef# controlled program operation timing diagrams, and figure 24 for flow- charts. during the program operation, the only valid flash read operations are data# polling and toggle bit. during the internal program operation, the host is free to perform addi- tional tasks. during the command sequence, wp# should be statically held high or low. any sdp commands loaded during the internal program operation will be ignored. concurrent read/write state table flash psram program/erase read program/erase write
preliminary specifications multi-purpose flash plus + psram combomemory sst32hf64a2 3 ?2007 silicon storage technology, inc. s71299-03-000 7/07 flash sector/block- erase operation the sst32hf64a2 offers both sector-erase and block- erase operations. the flash sector/block-erase operation erases the device on a sector-by-sector (or block-by-block) basis. the sector architecture is based on uniform sector size of 2 kword. the block-erase mode is based on uni- form block size of 32 kword. initiate the sector-erase operation by executing a six-byte command sequence with sector-erase command (50h) and sector address (sa) in the last bus cycle. the address lines a ms -a 11 are used to determine the sector address. initiate the block-erase operation by executing a six-byte command sequence with block-erase command (30h) and block address (ba) in the last bus cycle. the address lines a ms -a 15 are used to determine the block address. the sector or block address is latched on the falling edge of the sixth we# pulse, while the command (30h or 50h) is latched on the rising edge of the sixth we# pulse. erase operations begin after the sixth we# pulse. the end-of-erase operation can be determined using either data# polling or toggle bit methods. see figures 13 and 14 for timing waveforms. any commands issued during the sector- or block-erase operation are ignored, wp# should be statically held high or low. erase-suspend/erase- resume commands the erase-suspend operation temporarily suspends a sector- or block-erase operation allowing data to be read from any memory location, or programed to any sector/ block that is not suspended for an erase operation. exe- cute the operation by issuing a one byte command sequence with erase-suspend command (b0h). the device automatically enters read mode typically within 20 s after the erase-suspend command had been issued. valid data can be read from any sector or block that is not suspended from an erase operation. reading at address location within erase-suspended sectors/blocks will output dq 2 toggling and dq 6 at ?1?. while in erase-suspend mode, a word-program operation is allowed except for the sector or block selected for erase-suspend. to resume the sector-erase or block-erase operation which has been suspended, the system must issue the erase resume command. execute the operation by issu- ing a one byte command sequence with erase-resume command (30h) at any address in the last byte sequence. flash chip-erase operation the sst32hf64a2 provides a chip-erase operation, which allows the user to erase the entire memory array to the ?1? state. this is useful when the entire device must be quickly erased. initiate the chip-erase operation executing a six- byte com- mand sequence with chip-erase command (10h) at address 555h in the last byte sequence. the erase opera- tion begins with the rising edge of the sixth we# or bef#, whichever occurs first. during the erase operation, the only valid read is toggle bit or data# polling. see table 6 for the command sequence, figure 11 for timing diagram, and figure 28 for the flowchart. any commands issued during the chip-erase operation are ignored. write operation status detection the sst32hf64a2 provides two software means to detect the completion of a write (program or erase) cycle, in order to optimize the system write cycle time. the software detection includes two status bits: data# polling (dq 7 ) and to g g l e b i t ( d q 6 ). the end-of-write detection mode is enabled after the rising edge of we#, which initiates the internal program or erase operation. the actual completion of the nonvolatile write is asynchro- nous with the system; therefore, either a data# polling or toggle bit read may be simultaneous with the completion of the write cycle. if this occurs, the system may get an erroneous result, i.e., valid data may appear to conflict with either dq 7 or dq 6. to prevent spurious rejection, in the event of an erroneous result, the software routine must include a loop to read the accessed location an additional two (2) times. if both reads are valid, then the device has completed the write cycle, otherwise the rejection is valid.
4 preliminary specifications multi-purpose flash plus + psram combomemory sst32hf64a2 ?2007 silicon storage technology, inc. s71299-03-000 7/07 flash data# polling (dq 7 ) when the sst32hf64a2 flash memory banks are in the internal program operation, any attempt to read dq 7 will produce the complement of the true data. once the pro- gram operation is complete, dq 7 will produce true data. however, even though dq 7 may have valid data immedi- ately following the completion of an internal write opera- tion, the remaining data outputs may still be invalid. valid data on the entire data bus will appear in subsequent suc- cessive read cycles after an interval of 1 s. during internal erase operation, any attempt to read dq 7 will produce a ?0?. once the internal erase operation is complete, dq 7 will produce a ?1?. the data# polling is valid after the rising edge of the fourth we# (or bef#) pulse for program operation. for sector- or block-erase, the data# polling is valid after the rising edge of the sixth we# (or bef#) pulse. see figure 10 for data# polling timing dia- gram and figure 25 for a flowchart. toggle bits (dq6 and dq2) during the internal program or erase operation, any con- secutive attempts to read dq 6 bit will alternate between ?1? and ?0?. when the internal program or erase operation is complete, the dq 6 bit will stop toggling. the device is then ready for the next operation. for sector-, block-, or chip-erase, the toggle bit (dq 6 ) is valid after the rising edge of sixth we# (or bef#) pulse. dq 6 will be set to ?1? if a read operation is attempted on an erase-suspended sector/block. if a program operation is initiated in a sector/block not selected in erase-suspend mode, dq 6 will toggle. an additional toggle bit is available on dq 2 , which is used in conjunction with dq 6 to check whether a particular sec- tor is being actively eras ed or erase-suspended. table 1 shows detailed status bits information. the toggle bit (dq 2 ) is valid after the rising edge of the last we# (or bef#) pulse of write operation. see figure 11 for toggle bit timing diagram and figure 25 for a flowchart. note: dq 7 and dq 2 require a valid address when reading status information. flash memory data protection the sst32hf64a2 flash memory bank provides both hardware and software features to protect nonvolatile data from inadvertent writes. flash hardware data protection noise/glitch protection : a we# or bef# pulse of less than 5 ns will not initiate a write cycle. v dd power up/down detection: the write operation is inhibited when v dd is less than 1.5v. write inhibit mode: forcing oe# low, bef# high, or we# high will inhibit the flash write operation. this prevents inadvertent writes during power-up or power-down. table 1: write operation status status dq 7 dq 6 dq 2 normal operation standard program dq 7 # toggle no toggle standard erase 0 toggle toggle erase- suspend mode read from erase-suspended sector/block 1 1 toggle read from non- erase-suspended sector/block data data data program dq 7 # toggle n/a t1.0 1299
preliminary specifications multi-purpose flash plus + psram combomemory sst32hf64a2 5 ?2007 silicon storage technology, inc. s71299-03-000 7/07 hardware block protection the sst32hf64a2 supports top hardware block protec- tion, which protects the top 32 kword block of the device. the boot block address ranges are described in table 2. program and erase operations are prevented on the 32 kword when wp# is low. if wp# is left floating, it is inter- nally held high via a pull-up resistor, and the boot block is unprotected, enabling program and erase operations on that block. hardware reset (rst#) the rst# pin provides a hardware method of resetting the device to read array data. when the rst# pin is held low for at least t rp, any in-progress operat ion will terminate and return to read mode. when no internal program/erase operation is in progress, a minimum period of t rhr is required after rst# is driven high before a valid read can take place (see figure 19). the erase or program operation that has been interrupted needs to be reinitiated after the device resumes normal operation mode to ensure data integrity. flash software data protection (sdp) the sst32hf64a2 provides the jedec approved soft- ware data protection scheme for all flash memory bank data-alteration operations, i.e., program and erase. any program operation requires a three-byte sequence series. using the three byte-load sequence to initiate the program operation, provides optimal protection from inadvertent write operations, e.g., during the system power-up or power-down. any erase operation requires a six-byte load sequence. the sst32hf64a2 devices are shipped with the software data protection permanently enabled. see table 6 for the specific software command codes. during sdp command sequence, invalid commands will abort the device to read mode, within t rc. the contents of dq 15 -dq 8 can be v il or v ih, but no other value, during any sdp command sequence. common flash memory interface (cfi) the sst32hf64a2 contains the cfi information which describes the characteristics of the device. in order to enter the cfi query mode, the system must write a three-byte sequence, the same as the product id entry command, with 98h (cfi query command) to address 555h in the last byte sequence. once the device enters the cfi query mode, the system reads the cfi data at the addresses given in tables 7 through 9. the system must write the cfi exit command to return to read mode from the cfi query mode. table 2: boot block address ranges product address range top boot block sst32hf64a2 3f8000h-3fffffh t2.0 1299
6 preliminary specifications multi-purpose flash plus + psram combomemory sst32hf64a2 ?2007 silicon storage technology, inc. s71299-03-000 7/07 product identification the product identification mode identifies the device as the sst32hf64a2 and manufacturer as sst. this mode is accessed by software operations only. the hardware device id read operation, which is typically used by programmers, cannot be used on this device because of the shared lines between flash and psram in the multi-chip package. therefore, application of high volt- age to pin a 9 may damage this device. use the software product identification operation to identify the part (i.e., using the device id) when using multiple man- ufacturers in the same socket. for details, see tables 5 and 6 for software operation, figure 15 for the software id entry and read timing diagram and figure 26 for the id entry command sequence flowchart. product identification mode exit/ cfi mode exit to return to the standard read mode, the software product identification mode and cfi mode must be exited. exit by issuing the exit id command sequence which returns the device to the read operation. however, the id exit/cfi exit command is ignored during an internal program or erase operation. this command may also be used to reset the device to read mode after any inadvertent transient condi- tion that apparently causes the device to behave abnor- mally, e.g. not read correctly. see table 6 for software command codes, figure 16 for timing waveform and figure 26 for a flowchart. security id the sst32hf64a2 device offers a 256-bit security id space. the secure id space is divided into two 128-bit seg- ments - one factory programmed segment and one user programmed segment. the first segment is programmed and locked at sst with a random 128-bit number. the user segment is left un-programmed for the customer to pro- gram as desired. use the security id word-program to program the user segment of the security id. to detect end-of-write for the sec id, read the toggle bits, no t data# polling. once this is complete, the sec id is locked using the user sec id pro- gram lock-out. this disables any future corruption of this space. regardless of whether or not the sec id is locked, neither sec id segment can be erased. the secure id space can be queried by executing a three- byte command sequence with enter sec id command (88h) at address 555h in the last byte sequence. to exit this mode, the exit sec id command should be executed. refer to table 6 for more details. psram deep po wer-down mode the psram deep power-down mode is used to lower the power consumption of the psram in the sst32hf64a2. deep power-down occurs 1 s after being enabled by driv- ing bes2 low. normal operation occurs 500 s after driving bes2 high. in deep power-down mode, psram data is lost. see figure 23 for the state diagram. psram read the psram read operation of the sst32hf64a2 is con- trolled by oe# and bes1#, both have to be low with we# and bes2 high for the system to obtain data from the out- puts. oe# is the output control and is used to gate data from the output pins. the data bus is in high impedance state when oe# is high. refer to the read cycle timing dia- gram, figure 4, for further details. psram write the psram write operation of the sst32hf64a2 is con- trolled by we# and bes1#, both have to be low, bes2 must be high for the system to write to the psram. during the word-write operation, the addresses and data are ref- erenced to the rising edge of either bes1# or we#, which- ever occurs first. the write time is measured from the last falling edge of bes1# or we# to the first rising edge of bes1# or we#. refer to the write cycle timing diagrams, figures 5 and 6, for further details. design considerations sst recommends a high frequency 0.1 f ceramic capac- itor to be placed as close as possible between v dd and v ss , e.g., less than 1 cm away from the v dd pin of the device. additionally, a low frequency 4.7 f electrolytic capacitor from v dd to v ss should be placed within 1 cm of the v dd pin. table 3: product identification address data manufacturer?s id 0000h bfh device id sst32hf64a2 0001h 236ch t3.0 1299
preliminary specifications multi-purpose flash plus + psram combomemory sst32hf64a2 7 ?2007 silicon storage technology, inc. s71299-03-000 7/07 functional block diagram figure 1: functional block diagram i/o buffers 1299 b1.0 address buffers dq 15 - dq 8 a ms -a 0 we# 1 superflash memory psram control logic bes1# bes2 bef# oe# 1 reset# wp# address buffers & latches lbs# ubs# dq 7 - dq 0 note: 1. for ls package only: we# = wef# and/or wes# oe # = oef# and/or oes#
8 preliminary specifications multi-purpose flash plus + psram combomemory sst32hf64a2 ?2007 silicon storage technology, inc. s71299-03-000 7/07 pin description figure 2: pin assignments for 64-ball lfbga (8mm x 10mm) figure 3: pin assignments for 56-ball lfbga (8mm x 10mm) 1299 64-lfbga l2s p2.0 nc nc a20 a16 wef# v sss wp# lbs# a18 nc a11 a8 nc rst# nc ubs# a17 a5 a15 a10 a21 nc a19 oes# a7 a4 a14 a9 dq11 a6 a0 a13 dq15 dq13 dq12 dq9 a3 bef# a12 wes# dq6 bes2 dq10 dq8 a2 v ssf v ssf dq14 dq4 v dds dq2 dq0 a1 oef# nc dq7 dq5 v ddf dq3 dq1 bes1# nc nc nc a b c d e f g h j k 8 7 6 5 4 3 2 1 top view (balls facing down) 1299 56-lfbga l1p p3.0 a11 a8 we# wp# lbs# a7 a15 a12 a19 bes2 rst# ubs# a6 a3 a21 a13 a9 a20 nc a18 a5 a2 nc a14 a10 a17 a4 a1 a16 nc dq6 dq1 v ss a0 nc dq15 dq13 dq4 dq3 dq9 oe# bef# v ss dq7 dq12 v dds v ddf dq10 dq0 bes1# dq14 dq5 nc dq11 dq2 dq8 a b c d e f g h 8 7 6 5 4 3 2 1 top view (balls facing down)
preliminary specifications multi-purpose flash plus + psram combomemory sst32hf64a2 9 ?2007 silicon storage technology, inc. s71299-03-000 7/07 table 4: pin description symbol pin name functions a ms 1 to a 0 address inputs to provide flash address, a 21 -a 0 . a mss 1 to a 0 address inputs to provide psram address, a 19 -a 0 dq 15 -dq 0 data inputs/outputs to output da ta during read cycles and receive input data during write cycles. data is internally latche d during a flash er ase/program cycle. the outputs are in tri-state when oe# is high or bes1# is high or bes2 is low and bef# is high. bef# flash memory bank enable to activate the flash memory bank when bef# is low bes1# psram memory bank enable to activate the psram memory bank when bes1# is low bes2 psram deep power-down enable to activate the psram memory deep power-down mode when bes2 is v il oef# 2 output enable to gate the data output buffers for flash only oes# 2 output enable to gate the data output buffers for psram only wef# 2 write enable to control the wr ite operations for flash only wes# 2 write enable to control the wr ite operations for psram only oe# output enable to gate the data output buffers we# write enable to control the write operations ubs# upper byte control (psram) to enable dq 15 -dq 8 lbs# lower byte control (psram) to enable dq 7 -dq 0 wp# write protect to protect and unprotect se ctors from erase or program operation rst# reset to reset and return the device to read mode v ssf 2 ground flash only 2 v sss 2 ground psram only 2 v ss ground v dd f power supply (flash) 2.7-3.3v power supply to flash only v dd s power supply (psram) 2.7-3.3v power supply to psram only nc no connection unconnected pins t4.0 1299 1. a ms = most significant flash address a mss = most significant psram address 2. for l2s package only
10 preliminary specifications multi-purpose flash plus + psram combomemory sst32hf64a2 ?2007 silicon storage technology, inc. s71299-03-000 7/07 table 5: operational modes selection 1 mode bef# 2 bes1# 2 bes2 oe# 3 we# 3 lbs# ubs# dq 7-0 dq 15-8 full standby v ih v ih v ih x x x x high-z high-z psram deep power-down 4 v ih v il v il x x x x high-z high-z output disable v ih v il v ih v ih v ih x x high-z high-z v il v ih v ih v ih v ih x x high-z high-z flash read v il v ih v ih v il v ih xxd out d out flash write v il v ih v ih v ih v il xx d in d in flash erase v il v ih v ih v ih v il xx x x psram read v ih v il v ih v il v ih v il v il d out d out v ih v il high-z d out v il v ih d out high-z psram write v ih v il v ih xv il v il v il d in d in v ih v il high-z d in v il v ih d in high-z product identification 5 v il v ih v ih v il v ih x x manufacturer?s id 6 device id 6 t5.0 1299 1. x can be v il or v ih , but no other value. 2. for sst32hf64a2, to avoid bus contention do not apply bef# = v il and bes1# = v il at the same time 3. oe# = oef# and oes# we# = wef# and wes# 4. in psram deep power-down, psram data is lost. 5. software mode only 6. with a 21 -a 1 = 0; sst manufacturer?s id = 00bfh, is read with a 0 =0, sst32hf64a2 device id = 236ch, is read with a 0 =1.
preliminary specifications multi-purpose flash plus + psram combomemory sst32hf64a2 11 ?2007 silicon storage technology, inc. s71299-03-000 7/07 table 6: software command sequence command sequence 1st bus write cycle 2nd bus write cycle 3rd bus write cycle 4th bus write cycle 5th bus write cycle 6th bus write cycle addr 1 data 2 addr 1 data 2 addr 1 data 2 addr 1 data 2 addr 1 data 2 addr 1 data 2 word-program 555h aah 2aah 55h 555h a0h wa 3 data sector-erase 555h aah 2aah 55h 555h 80h 555h aah 2aah 55h sa x 4 50h block-erase 555h aah 2aah 55h 555h 80h 555h aah 2aah 55h ba x 4 30h chip-erase 555h aah 2aah 55h 555h 80h 555h aah 2aah 55h 555h 10h erase-suspend xxxxh b0h erase-resume xxxxh 30h query sec id 5 555h aah 2aah 55h 555h 88h user security id word-program 555h aah 2aah 55h 555h a5h wa 6 data cfi query entry 555h aah 2aah 55h 555h 98h user security id program lock-out 555h aah 2aah 55h 555h 85h xxh 6 0000h software id entry 7,8 555h aah 2aah 55h 555h 90h software id exit 9,10 /sec id exit/cfi exit 555h aah 2aah 55h 555h f0h software id exit 9,10 /sec id exit/cfi exit xxh f0h t6.0 1299 1. address format a 11 -a 0 (hex). addresses a 12 -a 21 can be v il or v ih , but no other value, for command sequence for sst32hf64a2. 2. dq 15 -dq 8 can be v il or v ih , but no other value, for command sequence 3. wa = program word address 4. sa x for sector-erase; uses a ms -a 11 address lines ba x , for block-erase; uses a ms -a 15 address lines a ms = most significant address a ms = a 21 for sst32hf64a2. 5. with a ms -a 4 = 0; sec id is read with a 3 -a 0 , sst id is read with a 3 = 0 (address range = 000000h to 000007h), user id is read with a 3 = 1 (address range = 000010h to 000017h). lock status is read with a 7 -a 0 = 0000ffh. unlocked: dq 3 = 1 / locked: dq 3 = 0. 6. valid word-addresses for sec id are from 000000h-000007h and 000010h-000017h. 7. the device does not remain in software product id mode if powered down. 8. with a ms -a 1 =0; sst manufacturer id = 00bfh, is read with a 0 = 0, sst32hf64a2 device id = 236ch, is read with a 0 =1. a ms = most significant address a ms = a 21 for sst32hf64a2. 9. both software id exit operations are equivalent 10. if users never lock after programming, sec id can be programm ed over the previously unprogramm ed bits (data=1) using the sec id mode again (the programmed ?0? bits cannot be reversed to ?1?). valid word-addresses for sec id are from 000000h-000007h and 000010h-000017h.
12 preliminary specifications multi-purpose flash plus + psram combomemory sst32hf64a2 ?2007 silicon storage technology, inc. s71299-03-000 7/07 table 7: cfi query identification string 1 for sst32hf64a2 address data data 10h 0051h query unique ascii string ?qry? 11h 0052h 12h 0059h 13h 0002h primary oem command set 14h 0000h 15h 0000h address for primary extended table 16h 0000h 17h 0000h alternate oem command set (00h = none exists) 18h 0000h 19h 0000h address for alternate oem extended table (00h = none exits) 1ah 0000h t7.0 1299 1. refer to cfi publication 100 for more details. table 8: system interface information for sst32hf64a2 address data data 1bh 0027h v dd min (program/erase) dq 7 -dq 4 : volts, dq 3 -dq 0 : 100 millivolts 1ch 0036h v dd max (program/erase) dq 7 -dq 4 : volts, dq 3 -dq 0 : 100 millivolts 1dh 0000h v pp min. (00h = no v pp pin) 1eh 0000h v pp max. (00h = no v pp pin) 1fh 0003h typical time out for word-program 2 n s (2 3 = 8 s) 20h 0000h typical time out for min. size buffer program 2 n s (00h = not supported) 21h 0004h typical time out for individual sector/block-erase 2 n ms (2 4 = 16 ms) 22h 0005h typical time out for chip-erase 2 n ms (2 5 = 32 ms) 23h 0001h maximum time out for word-program 2 n times typical (2 1 x 2 3 = 16 s) 24h 0000h maximum time out for buffer program 2 n times typical 25h 0001h maximum time out for individual sector/block-erase 2 n times typical (2 1 x 2 4 = 32 ms) 26h 0001h maximum time out for chip-erase 2 n times typical (2 1 x 2 5 = 64 ms) t8.0 1299 table 9: device geometry information for sst32hf64a2 address data data 27h 0017h device size = 2 n bytes (17h = 23; 2 23 = 8 mbyte) 28h 0001h flash device interface description; 0001h = x16-only asynchronous interface 29h 0000h 2ah 0000h maximum number of bytes in multi-byte write = 2 n (00h = not supported) 2bh 0000h 2ch 0002h number of erase sector/block sizes supported by device 2dh 00ffh sector information (y + 1 = numb er of sectors; z x 256b = sector size) 2eh 0007h y = 2047 + 1 = 2048 sectors (07ffh = 2047) 2fh 0010h 30h 0000h z = 16 x 256 bytes = 4 kbytes/sector (0010h = 16) 31h 007fh block information (y + 1 = number of blocks; z x 256b = block size) 32h 0000h y =127 + 1 = 128 blocks (007fh = 127) 33h 0000h 34h 0001h z = 256 x 256 bytes = 64 kbytes/block (0100h = 256) t9.0 1299
preliminary specifications multi-purpose flash plus + psram combomemory sst32hf64a2 13 ?2007 silicon storage technology, inc. s71299-03-000 7/07 absolute maximum stress ratings (applied conditions greater than t hose listed under ?absolute maximum stress ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these conditions or conditions greater t han those defined in the operational sections of this data sheet is not implied. exposu re to absolute maximum stress rating co nditions may affect device reliability.) operating temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -20c to +85c storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65c to +150c d. c. voltage on any pin to ground potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5v to v dd 1 +0.3v transient voltage (<20 ns) on any pin to ground potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1.0v to v dd 1 +1.0v package power dissipation capability (t a = 25c) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0w surface mount solder reflow temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260c for 10 seconds output short circuit current 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 ma 1. v dd = v ddf and v dds 2. outputs shorted for no more than one second. no more than one output shorted at a time. operating range range ambient temp v dd extended -20c to +85c 2.7-3.3v ac conditions of test input rise/fall time . . . . . . . . . . . . . . 5 ns output load . . . . . . . . . . . . . . . . . . . . c l = 30 pf see figures 21 and 22
14 preliminary specifications multi-purpose flash plus + psram combomemory sst32hf64a2 ?2007 silicon storage technology, inc. s71299-03-000 7/07 table 10: dc operating characteristics (v dd = v ddf and v dds = 2.7-3.3v) symbol parameter limits test conditions min max units i dd active v dd current address input = v ilt /v iht, at f=5 mhz, v dd =v dd max, all dqs open read oe#=v il , we#=v ih flash 18 ma bef#=v il , bes1#=v ih , or bes2=v il psram 30 ma bef#=v ih , bes1#=v il , bes2=v ih concurrent operation 40 ma bef#=v ih , bes1#=v il , bes2=v ih write 1 we#=v il flash 35 ma bef#=v il , bes1#=v ih , or bes2=v il , oe#=v ih psram 30 ma bef#=v ih , bes1#=v il , bes2=v ih i sb standby v dd current 135 a v dd = v dd max, bef#=bes1#=v ihc , bes2=v ihc i sbp deep power down: psram 10 a bes2=v ilc, bef#=v ihc i rt reset v dd current 30 a reset=v ss 0.3v i li input leakage current 1 a v in =gnd to v dd , v dd =v dd max i lo output leakage current 10 a v out =gnd to v dd , v dd =v dd max v il input low voltage 0.8 v v dd =v dd min v ilc input low voltage (cmos) 0.2 v v dd =v dd max v ih input high voltage 0.7 v dd vv dd =v dd max v ihc input high voltage (cmos) v dd -0.3 v v dd =v dd max v olf flash output low voltage 0.2 v i ol =100 a, v dd =v dd min v ohf flash output high voltage v dd -0.2 v i oh =-100 a, v dd =v dd min v ols psram output low voltage 0.4 v i ol =1 ma, v dd =v dd min v ohs psram output high voltage 2.2 v i ol =-500 a, v dd =v dd min t10.0 1299 1. i dd active while erase or program is in progress.
preliminary specifications multi-purpose flash plus + psram combomemory sst32hf64a2 15 ?2007 silicon storage technology, inc. s71299-03-000 7/07 table 11: recommended system power-up timings symbol parameter minimum units t pu-read 1 power-up to read operation 100 s t pu-write 1 power-up to program/erase operation 100 s t11.0 1299 1. this parameter is measured only for init ial qualification and after a design or proc ess change that could affect this paramet er. table 12: capacitance (t a = 25c, f=1 mhz, other pins open) parameter description test condition maximum c i/o 1 1. this parameter is measured only for init ial qualification and after a design or proc ess change that could affect this paramet er. i/o pin capacitance v i/o = 0v 12 pf c in 1 input capacitance v in = 0v 12 pf t12.0 1299 table 13: flash reliability characteristics symbol parameter minimum spec ification units test method n end 1 1. this parameter is measured only for init ial qualification and after a design or proc ess change that could affect this paramet er. endurance 10,000 cycles jedec standard a117 t dr 1 data retention 100 years jedec standard a103 i lt h 1 latch up 100 + i dd ma jedec standard 78 t13.0 1299
16 preliminary specifications multi-purpose flash plus + psram combomemory sst32hf64a2 ?2007 silicon storage technology, inc. s71299-03-000 7/07 ac characteristics table 14: psram read cycle timing parameters symbol parameter min max units t rcs read cycle time 70 ns t aas address access time 70 ns t bes bank enable access time 70 ns t oes output enable access time 35 ns t byes ubs#, lbs# access time 70 ns t blzs 1 1. this parameter is measured only for init ial qualification and after a design or proc ess change that could affect this paramet er. bes1# to active output 0 ns t olzs 1 output enable to active output 0 ns t bylzs 1 ubs#, lbs# to active output 0 ns t bhzs 1 bes1# to high-z output 25 ns t ohzs 1 output disable to high-z output 0 25 ns t byhzs 1 ubs#, lbs# to high-z output 35 ns t ohs output hold from address change 10 ns t14.0 1299 table 15: psram write cy cle timing parameters symbol parameter min max units t wcs write cycle time 70 ns t bws bank enable to end-of-write 60 ns t aws address valid to end-of-write 60 ns t asts address set-up time 0 ns t wps write pulse width 60 ns t wrs write recovery time 0 ns t byws ubs#, lbs# to end-of-write 60 ns t odws output disable from we# low 30 ns t oews output enable from we# high 0 ns t dss data set-up time 30 ns t dhs data hold from write time 0 ns t15.0 1299
preliminary specifications multi-purpose flash plus + psram combomemory sst32hf64a2 17 ?2007 silicon storage technology, inc. s71299-03-000 7/07 table 16: flash read cycle timing parameters v dd = 2.7-3.6v symbol parameter min max units t rc read cycle time 70 ns t ce chip enable access time 70 ns t aa address access time 70 ns t oe output enable access time 35 ns t clz 1 bef# low to active output 0 ns t olz 1 oe# low to active output 0 ns t chz 1 bef# high to high-z output 20 ns t ohz 1 oe# high to high-z output 20 ns t oh 1 output hold from address change 0 ns t rp 1 rst# pulse width 500 ns t rhr 1 rst# high before read 50 ns t ry 1,2 rst# pin low to read mode 20 s t16.0 1299 1. this parameter is measured only for init ial qualification and after a design or proc ess change that could affect this paramet er. 2. this parameter applies to sector-erase, block-erase and program operations. this parameter does not apply to chip-erase operations. table 17: flash program/erase cycle timing parameters symbol parameter min max units t bp word-program time 10 s t as address setup time 0 ns t ah address hold time 30 ns t cs we# and bef# setup time 0 ns t ch we# and bef# hold time 0 ns t oes oe# high setup time 0 ns t oeh oe# high hold time 10 ns t cp bef# pulse width 40 ns t wp we# pulse width 40 ns t wph 1 1. this parameter is measured only for init ial qualification and after a design or proc ess change that could affect this paramet er. we# pulse width high 30 ns t cph 1 bef# pulse width high 30 ns t ds data setup time 30 ns t dh 1 data hold time 0 ns t ida 1 software id access and exit time 150 ns t se sector-erase 25 ms t be block-erase 25 ms t sce chip-erase 50 ms t17.0 1299
18 preliminary specifications multi-purpose flash plus + psram combomemory sst32hf64a2 ?2007 silicon storage technology, inc. s71299-03-000 7/07 figure 4: psram read cycle ti ming diagram for sst32hf64a2 addresses a mss-0 dq 15-0 ubs#, lbs# oe# bes1# t rcs t aas t bes t oes t blzs t olzs t byes t bylzs t byhzs data valid t ohzs t bhzs t ohs 1299 f03b.0 note: a mss = most significant psram address a mss = a 19 for sst32hf64a2
preliminary specifications multi-purpose flash plus + psram combomemory sst32hf64a2 19 ?2007 silicon storage technology, inc. s71299-03-000 7/07 figure 5: psram write cycle timing diag ram for sst32hf64a2 (we# controlled) 1 t aws addresses a mss 3 -0 bes1# we# ubs#, lbs# t wps t wrs t wcs t asts t bws t byws t odws t oews t dss t dhs 1299 f04b.0 note 2 note 2 dq 15-8, dq 7-0 valid data in note: 1. if oe# is high during the write cycle, t he outputs will remain at high impedance. 2. if bes1# goes low coincident with or after we# goes low, the output will remain at high impedance. if bes1# goes high coincident with or before we# goes high, the output will remain at high impedance. because d in signals may be in the output state at this time, input signals of reverse polarity must not be applied. 3. a mss = most significant psram address a mss = a 19 for sst32hf64a2
20 preliminary specifications multi-purpose flash plus + psram combomemory sst32hf64a2 ?2007 silicon storage technology, inc. s71299-03-000 7/07 figure 6: psram write cycle timing diagram (ubs#, lbs# controlled) 1 addresses a mss 3 -0 we# bes1# bes2 t bws t bws t aws t wcs t wps t wrs t asts t byws dq 15-8, dq 7-0 valid data in note 2 note 2 t dss t dhs ubs#, lbs# 1299 f05.0 note: 1. if oe# is high during the write cycle, t he outputs will remain at high impedance. 2. because d in signals may be in the output state at this time, input signals of reverse polarity must not be applied. 3. a mss = most significant psram address a mss = a 19 for sst32hf64a2
preliminary specifications multi-purpose flash plus + psram combomemory sst32hf64a2 21 ?2007 silicon storage technology, inc. s71299-03-000 7/07 figure 7: flash read cycle timing diagram figure 8: flash we# controlled program cycle timing diagram 1299 f06.0 address a ms-0 dq 15-0 we# oe# bef# t ce t rc t aa t oe t olz v ih high-z t clz t oh t chz high-z data valid data valid t ohz note: a ms = most significant flash address a ms = a 21 for sst32hf64a2 1299 f07.0 address a ms-0 dq 15-0 t dh t wph t ds t wp t ah t as t ch t cs bef# sw0 sw1 sw2 555 2aa 555 addr xxaa xx55 xxa0 data internal program operation starts word (addr/data) oe# we# t bp note: a ms = most significant flash address a ms = a 21 for sst32hf64a2 wp# must be held in proper logic state (v il or v ih ) 1 s prior to and 1 s after the command sequence x can be v il or v ih, but no other value
22 preliminary specifications multi-purpose flash plus + psram combomemory sst32hf64a2 ?2007 silicon storage technology, inc. s71299-03-000 7/07 figure 9: bef# controlled flash program cycle timing diagram figure 10: flash data# polling timing diagram 1299 f08.0 address a ms-0 dq 15-0 t dh t cph t ds t cp t ah t as t ch t cs we# sw0 sw1 sw2 555 2aa 555 addr xxaa xx55 xxa0 data internal program operation starts word (addr/data) oe# bef# t bp note: a ms = most significant flash address a ms = a 21 for sst32hf64a2 wp# must be held in proper logic state (v il or v ih ) 1 s prior to and 1 s after the command sequence x can be v il or v ih, but no other value 1299 f09.0 addresses a msf-0 dq 7 data data# data# data we# oe# bef# t oeh t oe t ce t oes note: a ms = most significant flash address a ms = a 21 for sst32hf64a2
preliminary specifications multi-purpose flash plus + psram combomemory sst32hf64a2 23 ?2007 silicon storage technology, inc. s71299-03-000 7/07 figure 11: flash toggle bit timing diagram figure 12: we# controlled flash chip-erase timing diagram 1299 f10.0 addresses a msf-0 dq 6 and dq 2 we# oe# bef# t oe t oeh t ce t oes two read cycles with same outputs note: a ms = most significant flash address a ms = a 21 for sst32hf64a2 1299 f11.0 address a ms-0 dq 15-0 we# sw0 sw1 sw2 sw3 sw4 sw5 555 2aa 2aa 555 555 xx55 xx10 xx55 xxaa xx80 xxaa 555 oe# bef# six-byte code for chip-erase t sce t wp note: a ms = most significant flash address a ms = a 21 for sst32hf64a2 wp# must be held in proper logic state (v il or v ih ) 1 s prior to and 1 s after the command sequence this device also supports bef# controlled chip-erase operation. the we# and bef# signals are interchangeable as l ong as minimum timings are meet. (see table 17) x can be v il or v ih, but no other value.
24 preliminary specifications multi-purpose flash plus + psram combomemory sst32hf64a2 ?2007 silicon storage technology, inc. s71299-03-000 7/07 figure 13: we# controlled flash block-erase timing diagram note: a ms = most significant flash address a ms = a 21 for sst32hf64a2 this device also supports bef# controlled block-erase operation. the we# and bef# signals are interchangeable as lo ng as minimum timings are meet. (see table 17.) ba x = block address wp# must be held in proper logic state (v il or v ih ) 1 s prior to and 1 s after the command sequence x can be v il or v ih, but no other value. 1299 f12.0 address a ms-0 dq 15-0 we# sw0 sw1 sw2 sw3 sw4 sw5 555 2aa 2aa 555 555 xx55 xx50 xx55 xxaa xx80 xxaa ba x oe# bef# six-byte code for block-erase t be t wp
preliminary specifications multi-purpose flash plus + psram combomemory sst32hf64a2 25 ?2007 silicon storage technology, inc. s71299-03-000 7/07 figure 14: we# controlled flash sector-erase timing diagram 1299 f13.0 address a ms-0 dq 15-0 we# sw0 sw1 sw2 sw3 sw4 sw5 555 2aa 2aa 555 555 xx55 xx30 xx55 xxaa xx80 xxaa sa x oe# bef# six-byte code for sector-erase t se t wp note: a ms = most significant flash address a ms = a 21 for sst32hf64a2 this device also supports bef# controlled sector-erase operation. the we# and bef# signals are interchangeable as l ong as minimum timings are meet. (see table 17.) sa x = sector address wp# must be held in proper logic state (v il or v ih ) 1 s prior to and 1 s after the command sequence x can be v il or v ih, but no other value.
26 preliminary specifications multi-purpose flash plus + psram combomemory sst32hf64a2 ?2007 silicon storage technology, inc. s71299-03-000 7/07 figure 15: software id entry and read figure 16: software id exit and reset/cfi exit 1299 f14.0 address a 14-0 t ida dq 15-0 we# sw0 sw1 sw2 mfg id 555 2aa 555 0000 0001 oe# bef# three-word sequence for software id entry t wp t wph t aa 00bf device id xx55 xxaa xx90 note: x can be v il or v ih, but no other value. wp# must be held in proper logic state (v il or v ih ) 1 s prior to and 1 s after the command sequence device id - see table 3 on page 6 1299 f15.0 address a 14-0 dq 15-0 t ida t wp t whp we# sw0 sw1 sw2 555 2aa 555 three-word sequence for software id exit/cfi exit oe# bef# xxaa xx55 xxf0 note: x can be v il or v ih, but no other value. wp# must be held in proper logic state (v il or v ih ) 1 s prior to and 1 s after the command sequence.
preliminary specifications multi-purpose flash plus + psram combomemory sst32hf64a2 27 ?2007 silicon storage technology, inc. s71299-03-000 7/07 figure 17: cfi query entry and read figure 18: flash sec id entry 1288 f12.0 address a 14-0 t ida dq 15-0 we# sw0 sw1 sw2 555 2aa 555 oe# ce# three-byte sequence for cfi query entry t wp t wph t aa xx55 xxaa xx98 note: wp# must be held in proper logic state (v il or v ih ) 1 s prior to and 1 s after the command sequence. x can be v il or v ih, but no other value. 1299 f16.0 address a msf-0 t ida dq 15-0 we# sw0 sw1 sw2 555 2aa 555 oe# bef# three-byte sequence for sec id entry t wp t wph t aa xx55 xxaa xx88 note: a ms = most significant flash address a ms = a 21 for sst32hf64a2 wp# must be held in proper logic state (v il or v ih ) 1 s prior to and 1 s after the command sequence. x can be v il or v ih, but no other value.
28 preliminary specifications multi-purpose flash plus + psram combomemory sst32hf64a2 ?2007 silicon storage technology, inc. s71299-03-000 7/07 figure 19: rst# timing diagram (when no internal operation is in progress) figure 20: rst# timing diagram (during program or erase operation) 1299 f17.0 rst# bef#/oe# t rp t rhr 1299 f18.0 rst# bef#/oe# t rp t ry end-of-write detection (toggle-bit)
preliminary specifications multi-purpose flash plus + psram combomemory sst32hf64a2 29 ?2007 silicon storage technology, inc. s71299-03-000 7/07 figure 21: ac input/output reference waveforms figure 22: a test load example 1299 f19.0 reference points output input v it v iht v ilt v ot ac test inputs are driven at v iht (v dd -0.2v) for a logic ?1? and v ilt (0.2v) for a logic ?0?. measurement reference points for inputs and outputs are v it (0.5 v dd ) and v ot (0.5 v dd ). input rise and fall times (10% ? 90%) are <5 ns. note: v it - v input te s t v ot - v output te s t v iht - v input high test v ilt - v input low test 1299 f20.0 to tester to dut c l
30 preliminary specifications multi-purpose flash plus + psram combomemory sst32hf64a2 ?2007 silicon storage technology, inc. s71299-03-000 7/07 figure 23: deep power-down state diagram 1299 dpdflwcht.0 power on initial state (wait 200 s) standby mode deep power-down mode active bes2 = v il power-up sequence deep power-down exit sequence bes1# = v ih or v il , bes2 = v ih bes1# = v ih or v il , bes2 = v ih bes1# = v il, bes2 = v ih, ubs# & lbs# and/or lbs# = v il bes2 = v ih, lbs# = v ih, bes1# = v ih or ubs# bes2 = v il
preliminary specifications multi-purpose flash plus + psram combomemory sst32hf64a2 31 ?2007 silicon storage technology, inc. s71299-03-000 7/07 figure 24: word-program algorithm 1299 f21.0 start write data: xxaah address: 555h write data: xx55h address: 2aah write data: xxa0h address: 555h write word address/word data wait for end of program (t bp , data# polling bit, or toggle bit operation) program completed note: x can be v il or v ih , but no other value
32 preliminary specifications multi-purpose flash plus + psram combomemory sst32hf64a2 ?2007 silicon storage technology, inc. s71299-03-000 7/07 figure 25: wait options 1299 f22.0 wait t bp , t sce, or t be program/erase initiated internal timer toggle bit ye s ye s no no program/erase completed does dq 6 match? read same word data# polling program/erase completed program/erase completed read word is dq 7 = true data? read dq 7 program/erase initiated program/erase initiated
preliminary specifications multi-purpose flash plus + psram combomemory sst32hf64a2 33 ?2007 silicon storage technology, inc. s71299-03-000 7/07 figure 26: software id/cfi entry command flowcharts 1288 f21.0 load data: xxaah address: 555h software product id entry command sequence load data: xx55h address: 2aah load data: xx90h address: 555h wait t ida read software id load data: xxaah address: 555h cfi query entry command sequence load data: xx55h address: 2aah load data: xx98h address: 555h wait t ida read cfi data load data: xxaah address: 555h sec id query entry command sequence load data: xx55h address: 2aah load data: xx88h address: 555h wait t ida read sec id x can be v il or v ih , but no other value
34 preliminary specifications multi-purpose flash plus + psram combomemory sst32hf64a2 ?2007 silicon storage technology, inc. s71299-03-000 7/07 figure 27: software id/cfi exit command flowcharts 1288 f22.0 load data: xxaah address: 555h software id exit/cfi exit/sec id exit command sequence load data: xx55h address: 2aah load data: xxf0h address: 555h load data: xxf0h address: xxh return to normal operation wait t ida wait t ida return to normal operation x can be v il or v ih , but no other value
preliminary specifications multi-purpose flash plus + psram combomemory sst32hf64a2 35 ?2007 silicon storage technology, inc. s71299-03-000 7/07 figure 28: erase command sequence 1299 f25.0 load data: xxaah address: 555h chip-erase command sequence load data: xx55h address: 2aah load data: xx80h address: 555h load data: xx55h address: 2aah load data: xx10h address: 555h load data: xxaah address: 555h wait t sce chip erased to ffffh load data: xxaah address: 555h sector-erase command sequence load data: xx55h address: 2aah load data: xx80h address: 555h load data: xx55h address: 2aah load data: xx50h address: sa x load data: xxaah address: 555h wait t se sector erased to ffffh load data: xxaah address: 555h block-erase command sequence load data: xx55h address: 2aah load data: xx80h address: 555h load data: xx55h address: 2aah load data: xx30h address: ba x load data: xxaah address: 555h wait t be block erased to ffffh note: x can be v il or v ih, but no other value.
36 preliminary specifications multi-purpose flash plus + psram combomemory sst32hf64a2 ?2007 silicon storage technology, inc. s71299-03-000 7/07 figure 29: concurrent operation flowchart 1299 f26.0 load sdp command sequence concurrent operation flash program/erase initiated wait for end of write indication flash operation completed end concurrent operation read or write psram end wait
preliminary specifications multi-purpose flash plus + psram combomemory sst32hf64a2 37 ?2007 silicon storage technology, inc. s71299-03-000 7/07 product ordering information valid combinations for sst32hf64a2 SST32HF64A2-70-4E-L2SE sst32hf64a2-70-4e-l1pe note: valid combinations are those products in mass producti on or will be in mass production. consult your sst sales representative to confirm availability of valid combinat ions and to determine availability of new combinations. device speed suffix1 suffix2 sst32 h f64a2 -70 -4e -x xxx environmental attribute e 1 = non-pb package modifier s = 64 ball positions p = 56 ball positions package type l2 = lfbga (8mm x 10mm x 1.4mm, 0.40mm ball size) l1 = lfbga (8mm x 10mm x 1.4mm, 0.45mm ball size) temperature range e = extended = -20c to +85c minimum endurance 4 = 10,000 cycles read access speed 70 = 70 ns hardware block protection 2 = top boot block psram density a = 16 mbit flash density 64 = 64 mbit voltage h = 2.7-3.3v product series 32 = mpf+ + psram combomemory 1. environmental suffix ?e? denotes non-pb solder. sst non-pb solder devices are ?rohs compliant?.
38 preliminary specifications multi-purpose flash plus + psram combomemory sst32hf64a2 ?2007 silicon storage technology, inc. s71299-03-000 7/07 packaging diagrams figure 30: 64-ball low-profile, fine-pitch ball grid array (lfbga) 8mm x 10mm sst package code: l2s a1 corner k j h g f e d c b a a b c d e f g h j k bottom view top view 8 7 6 5 4 3 2 1 8.00 0.10 0.40 0.05 (64x) a1 corner 10.00 0.10 0.80 5.60 0.80 7.20 64-lfbga-l2s-8x10-400mic-2.0 note: 1. although many dimensions are similar to those of jedec publication 95, mo-210, this specific package is not registered . 2. all linear dimensions are in millimeters. 3. coplanarity: 0.12 mm 4. ball opening size is 0.32 mm ( 0.05 mm) 8 7 6 5 4 3 2 1 1mm side view seating plane 0.32 0.05 1.30 0.10 0.12
preliminary specifications multi-purpose flash plus + psram combomemory sst32hf64a2 39 ?2007 silicon storage technology, inc. s71299-03-000 7/07 figure 31: 56-ball low-profile, fine-pitch ball grid array (lfbga) 8mm x 10mm sst package code: l1p h g f e d c b a a b c d e f g h side view 8 7 6 5 4 3 2 1 seating plane 0.35 0.05 1.30 0.10 0.12 0.45 0.05 (56x) 0.80 5.60 0.80 5.60 56-lfbga-l1p-8x10-450mic-4 note: 1. although many dimensions are similar to those of jedec publication 95, mo-210, this specific package is not registere d. 2. all linear dimensions are in millimeters. 3. coplanarity: 0.12 mm 4. ball opening size is 0.38 mm ( 0.05 mm) 8 7 6 5 4 3 2 1 1mm a1 corner bottom view top view 8.00 0.20 a1 corner 10.00 0.20
40 preliminary specifications multi-purpose flash plus + psram combomemory sst32hf64a2 ?2007 silicon storage technology, inc. s71299-03-000 7/07 table 18: revision history number description date 00 ? initial release of s71299 ? includes 64 mb devices and extended temperature mpns previously released in data sheets s71260 and s71261 ? removed 63-ball low-profile, fine-pitch ball grid array (lfbga) 8mm x 10mm dec 2005 01 ? changed i sb max limits to 135 a in dc operating characteristics table 10 page 13 apr 2006 02 ? removed sst32hf64a1, sst32hf64b1, and sst32hf64b2 (these part numbers were never produced.) ? added 56-ball low-profile, fine-pitch ball grid array (lfbga) 8mm x10mm ? revised a ms to a 0 and a mss to a 0 in pin assignment table 4 ? edited note 1 for pin assignment table 4 nov 2006 03 ? added ?common flash memory interface (cfi)? on page 5 ? moved psram info to page 6 ? added cfi query entry to table 6 on page 11 ? added cfi query table 7 on page 12 ? added system interface table 8 on page 12 ? added device geometry table 9 on page 12 ? added figure 16 ?cfi query entry and read? on page 27 ? changed 0.9v dd to v dd -0.2v and 01v dd to 0.2v in figure 21 on page 29 jul 2007 silicon storage technology, inc. ? 1171 sonora court ? sunnyvale, ca 94086 ? telephone 408-735-9110 ? fax 408-735-9036 www.superflash.com or www.sst.com

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